The present invention pertains to a method and apparatus for managing peripheral devices coupled to a bus, and more particularly, to a method and apparatus for handling abort conditions arising during accesses of peripheral devices in a Peripheral Component Interconnect (PCI) environment.
An example of a system implemented in a Peripheral Component Interconnect (PCI) architecture is shown in FIG. 1. A CPU 1 is coupled to a host bus 3 comprising signal lines for control, address, and data information. A first bridge circuit (also called a host bridge, host-to-PCI bridge, or North bridge circuit) 5 is coupled between the host bus and the PCI bus 7 comprising signal lines for control information and address/data information. The bridge circuit 5 contains cache controller circuitry and main memory controller circuitry to control accesses to cache memory 9 and main memory 11. Data from the main memory 11 can be transferred to/from the data lines of the host bus 3 and the address/data lines of the PCI bus 7 via the bridge circuit 5. A plurality of peripheral devices P1, P2, . . . are coupled to the PCI bus 7 which can be any of a variety of devices such as a SCSI host bus adapter, a LAN adapter, a graphics adapter, an audio peripheral device, etc. A second bridge circuit (also known as a South bridge) 15 is coupled between the PCI bus 7 and an expansion bus 17 such as an ISA or EISA bus. Coupled to the expansion bus are a plurality of peripheral devices such as a bus master 18, an I/O slave 19, and a memory slave 20. A bus master is a device that is capable of initiating a data transfer with another device.
The second bridge 15 typically contains one or more controllers for handling Direct Memory Access (DMA) between the main memory 11 and a peripheral coupled to the expansion bus 17. One such controller is the 82C37A-5 high performance programmable DMA controller manufactured by Intel Corporation of Santa Clara, Calif. A description of the operation of the 8237A controller can be found, for example, at pages 5-4 to 5-21 of the databook "Peripheral Components" .COPYRGT.1995 published by Intel Corporation, the disclosure of which is hereby incorporated by reference in its entirety. Two such 8237 controllers can be coupled together in a known manner to set up seven standard programming model DMA channels for seven devices coupled to the expansion bus 17 or PCI bus 7. As is also known in the art, the DMA controllers handle the I/O "handshaking" signals that exist on the expansion bus 17 and the PCI bus 7 when data is being transferred to/from the main memory 11 (for example) and the peripheral devices coupled to these busses 7, 17 without intervention by the CPU 1. The CPU 1 and the DMA controllers communicate via the control signal lines appearing on the host bus 3 and the PCI bus 7 through bridge 5.
In a typical DMA transfer between a peripheral device and the main memory 11, the CPU 1 first initiates registers in the DMA controller concerning the start address in main memory, the type of transfer (e.g., read or write operation), etc. These registers are assigned to a particular DMA channel, which in turn is assigned to the target peripheral device. Subsequent to the CPU access of the appropriate registers in the DMA controller, a DMA transfer takes place under the control of the DMA controller without further intervention by the CPU.
An enhancement to the DMA system described above is the Distributed Direct Memory Access (DDMA) system. A protocol for implementing DDMA for bus systems such as a PCI bus system has been promulgated by Compaq Computer Corporation and others entitled "Distributed DMA Support for PCI Systems" Revision 6.0, Sep. 1, 1995, the disclosure of which is hereby incorporated by reference in its entirety. In contrast to the DMA system, in a DDMA system, the independent, standard programming model Bus Master channels are distributed among peripheral devices, where these registers normally reside in the DMA controller in the DMA system described above. In other words, the registers associated with individual DMA channels can physically reside outside of the DMA controller in the second bridge circuit 15 and on devices coupled, for example, to the PCI bus 7. The effect is that when the CPU 1 attempts to access a distributed DMA channel, a DDMA Master component (not shown in FIG. 1) translates the PCI I/O reads and writes to the DMA I/O channel into reads and writes to a DMA Slave (e.g., an audio peripheral device). For this DDMA protocol, the DDMA Master component is defined which monitors signals appearing on the PCI bus 7. In a typical DDMA transfer, the CPU 1 continues to access the DMA controller in the second bridge circuit 15. If an access is attempted to a DMA channel that is distributed in some PCI peripheral, the DDMA Master collects or distributes the data before letting the CPU complete its accesses to the DMA channel. The DDMA Master will assert the necessary control signal(s) such that the CPU "thinks" that it is accessing a standard 8237-based design even though those registers are not located with the DMA controller(s).
There are several situations in which a peripheral will not respond during an access by the CPU or another bus master component. These situations include where: 1) the peripheral device is electrically shut off, 2) the peripheral is coupled to an additional PCI bus coupled to the PCI bus 7 and the additional PCI bus is physically detached from the PCI bus 7 (e.g., when a notebook computer is pulled out of a docking station) or the bridge circuit coupling the two busses together is not operating properly, 3) the clock to such an additional PCI bus is shut off, or 4) the peripheral is in a low power mode and is unable to respond. In a DDMA system or otherwise, if the peripheral device will not respond (i.e., it will not claim the transaction by asserting the DEVSEL# signal), the host bridge 5 (or the bus master in question) will perceive a Master Abort on the bus. During such a process the host bridge 5 will deassert the IRDY# signal line and return the bus to an idle state so that it is available for use by another bus master device. In executing a Master Abort, the PCI bus master must set its Master Abort Detected (or Received Master Abort) bit in its configuration status register.
The software that ultimately is seeking the transfer of data to/from the peripheral device may determine that the peripheral device is being accessed even though a Master Abort has occurred which can lead to errors in operation. Also, peripheral devices that are powered down cannot be accessed at all by another device until such time as the peripheral device is powered up. Accordingly, there is a need for a method and apparatus that provides for a peripheral device to be easily powered up so as to participate in PCI I/O without a significant loss of performance. There is also a need for a bus system architecture that provides for lower overall system power consumption. Furthermore, there is a need for a method and apparatus for managing peripheral devices that allows for determining causes for Master Abort errors that occur in a computer system.